Difference between revisions of "LAM 9400/Processes/LNF Poly"
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{{Infobox process | {{Infobox process | ||
|technology = RIE | |technology = RIE | ||
| − | |material = [[Polycrystalline_silicon|Poly]] | + | |material = [[Silicon|Si]], [[Polycrystalline_silicon|Poly]] |
|mask = [[Photoresist|PR]] | |mask = [[Photoresist|PR]] | ||
|gases = [[Hydrogen bromide|HBr]], [[Helium|He]] | |gases = [[Hydrogen bromide|HBr]], [[Helium|He]] | ||
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[[Category:Processes]] [[Category:RIE]] | [[Category:Processes]] [[Category:RIE]] | ||
| − | LNF_Poly | + | LNF_Poly can be used for etching Si, Polysilicon and GaAs. This process is fairly sensitive to the amount of open area of the wafer; the open area is the primary way to control the amount of sidewall passivation. This process is also used as the routine qualification for the LAM 9400. |
==Etch Rates== | ==Etch Rates== | ||
| − | *Si | + | * 5 min etch, Si wafer with SPR 955 mask, 22% open area |
| − | *SPR | + | ** Si: 181 nm/min |
| − | * | + | ** SPR 955 (0.9): 27 nm/min (6.7:1) |
| + | * SiO2 (6" SiO2 wafer): 15 nm/min | ||
| + | |||
| + | In general increasing the Si open area will slow the etch and increase the amount of passivation. The resist etch rate is also very dependent on the amount of open area. A piece on a SiO2 carrier vs a piece on a Si carrier will have drastically different resist etch rates (55 nm/min for SiO2 vs 24 nm/min for Si). | ||
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==Parameters== | ==Parameters== | ||
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==Sidewall Profile== | ==Sidewall Profile== | ||
| − | + | This etch can produce very vertical sidewall profiles, although trenches smaller then ~1µm will develop micro trenches as the etch progresses. | |
| + | |||
| + | <gallery mode="packed-hover" heights="250px"> | ||
| + | File:LAM_9400_LNF_Poly_300sec_22_open_3000nm_space_stripped.jpg|LNF_Poly for 300 sec, 22% open area, 3000nm Space, resist stripped | ||
| + | File:LAM_9400_LNF_Poly_300sec_22_open_1000nm_line_space_stripped.jpg|LNF_Poly for 300 sec, 22% open area, 1000nm Line/Space, resist stripped | ||
| + | File:LAM_9400_LNF_Poly_300sec_22_open_500nm_line_space_stripped.jpg|LNF_Poly for 300 sec, 22% open area, 500nm Line/Space, resist stripped | ||
| + | </gallery> | ||
| + | |||
| + | The sidewall passivation in this process is a SiOBr compound, and changing the amount of open area of Si is the main way to change the amount of passivation. With almost no exposed silicon the sidewall passivation will be very thin and the etch will be faster. | ||
| + | |||
| + | <gallery mode="packed-hover" heights="250px"> | ||
| + | File:LAM_9400_LNF_Poly_600sec_1_open_350nm_line.jpg|LNF_Poly for 600 sec, 1% open area, 350nm Line | ||
| + | File:LAM_9400_LNF_Poly_600sec_1_open_500nm_line_space.jpg|LNF_Poly for 600 sec, 1% open area, 500nm Line/Space | ||
| + | </gallery> | ||
| + | |||
| + | With a very high amount of open area the etch will be very over passivated. | ||
| − | <gallery mode="packed-hover" heights=" | + | <gallery mode="packed-hover" heights="250px"> |
| − | File: | + | File:LAM_9400_LNF_Poly_600sec_99_open_500nm_line.jpg|LNF_Poly for 600 sec, 99% open area, 500nm Line |
| − | File: | + | File:LAM_9400_LNF_Poly_600sec_99_open_500nm_line_space.jpg|LNF_Poly for 600 sec, 99% open area, 500nm Line/Space |
| + | File:LAM_9400_LNF_Poly_600sec_99_open_1000nm_line_space.jpg|LNF_Poly for 600 sec, 99% open area, 1000nm Line/Space | ||
</gallery> | </gallery> | ||
| − | == | + | ==Mask Removal== |
| − | + | To remove the photoresist a ~20 sec dip in 100:1 HF is necessary before nanostrip or piranah. | |
Latest revision as of 08:59, 22 August 2023
| About this Process | |
|---|---|
| Process Details | |
| Equipment | LAM 9400 |
| Technology | RIE |
| Material | Si, Poly |
| Mask Materials | PR |
| Gases Used | HBr, He |
| Date Created | 2016 |
LNF_Poly can be used for etching Si, Polysilicon and GaAs. This process is fairly sensitive to the amount of open area of the wafer; the open area is the primary way to control the amount of sidewall passivation. This process is also used as the routine qualification for the LAM 9400.
Etch Rates
- 5 min etch, Si wafer with SPR 955 mask, 22% open area
- Si: 181 nm/min
- SPR 955 (0.9): 27 nm/min (6.7:1)
- SiO2 (6" SiO2 wafer): 15 nm/min
In general increasing the Si open area will slow the etch and increase the amount of passivation. The resist etch rate is also very dependent on the amount of open area. A piece on a SiO2 carrier vs a piece on a Si carrier will have drastically different resist etch rates (55 nm/min for SiO2 vs 24 nm/min for Si).
Parameters
| Parameter | Breakthrough | Main Etch |
|---|---|---|
| Time | 10 sec | variable |
| Pressure | 5 mTorr | 30 mTorr |
| TCP Power | 300 W | 600 W |
| Bias Power | 100 W | 90 W |
| Cl2 Flow | 60 sccm | 0 sccm |
| HBr Flow | 0 sccm | 100 sccm |
| He Flow | 0 sccm | 100 sccm |
Sidewall Profile
This etch can produce very vertical sidewall profiles, although trenches smaller then ~1µm will develop micro trenches as the etch progresses.
LNF_Poly for 300 sec, 22% open area, 3000nm Space, resist stripped
LNF_Poly for 300 sec, 22% open area, 1000nm Line/Space, resist stripped
LNF_Poly for 300 sec, 22% open area, 500nm Line/Space, resist stripped
The sidewall passivation in this process is a SiOBr compound, and changing the amount of open area of Si is the main way to change the amount of passivation. With almost no exposed silicon the sidewall passivation will be very thin and the etch will be faster.
LNF_Poly for 600 sec, 1% open area, 350nm Line
LNF_Poly for 600 sec, 1% open area, 500nm Line/Space
With a very high amount of open area the etch will be very over passivated.
LNF_Poly for 600 sec, 99% open area, 500nm Line
LNF_Poly for 600 sec, 99% open area, 500nm Line/Space
LNF_Poly for 600 sec, 99% open area, 1000nm Line/Space
Mask Removal
To remove the photoresist a ~20 sec dip in 100:1 HF is necessary before nanostrip or piranah.
